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i am run under hassos node-red dock
my hdl bus ip 192.168.88.2
hassos ip 192.168.88.5
docker ip 172.17.0.3
I have everything set up, but when I link, I get the error
{"connected":true,"status":…
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Selecting 48 kHz will result in higher pitch and tempo, even if my audio devices are set to 48 kHz.
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Allowing to leave out signals that are not strictly required can increase the flexibility of the standard. As a point of reference, I believe only the tvalid signal is actually required in the AXI4 St…
olofk updated
2 years ago
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@vertrex, it looks like the reason you need 96MHz is because you are not using a double-line buffer, but a single line. I think you are trying to fill all the line data during blanking in a single buf…
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[VHDL/pyVHDLModel](https://github.com/VHDL/pyVHDLModel) is an abstract language model for VHDL, meant to be used as an interface between *any* VHDL parser and projects providing graphical views, refor…
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when i using catkin_make -DCMAKE_BUILD_TYPE=Release -DBUILD_VGICP_CUDA=ON, it occours:
CMake Error: The following variables are used in this project, but they are set to NOTFOUND.
Please set them …
whuzs updated
3 years ago
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Hi, i want to ask will hdl file for ZDMA's another fpga be published in the future?
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Hello,
I am using CMake as my build system for RTL simulations.
Very often I have a scenario where I have a custom command that would generate Verilog files.
I am using custom_commands rather tha…
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Se encuentra la información organizada y filtrada con el respectivo archivo de reporte de resultados:
https://uniandes.sharepoint.com/:f:/r/sites/UKPACT-GiroZero-GiroZeroGPS/Documentos%20compartido…