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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
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I followed the onload user guide to test two X2522 (installed on two work stations and connected directly by fibre).
I'm very sure there isn't any other tuned trick except '--profile=latency' I used.…
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Hello Team,
I am currently facing the Segmentation Issue while running the Python (Multi-Threaded) code for the resnet50
pre-trained model taken from the Vitis-AI Model-Zoo.
My Curr…
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I have a xilinx board zc706(xc7z045ffg900),i want to design a 10g nic , could i port corundum to this board , or what should i do for port corundum to this board, i have see my board only support pci…
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Hi.
I'm trying to run neptune example in alveo directory.
But in my environment, the example is not work.
I started server as typing "./run.sh" and I accessed :8998.
I was trying to start …
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When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate the board, and the blue li…
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Right now neither rustc nor cargo are being installed as part of the SDK build - this would probably be quite useful, especially for cross-compiling projects with mixed C/Rust environments.
I made …
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On the [MLIR-AIE](https://github.com/Xilinx/mlir-aie/tree/main) side, everything seems to be clear as long as it is to be run on VCK190. I understood that to make it on VCK5000, MLIR-AIR is needed. I …
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Hello,
I am encountering an issue while using **hls::stream** as an intermediate variable in my project. **The compiler is indicating that the bit width is too large, exceeding the 4096 limit.** He…
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In 'Profiling the Application' of section create my first SDAccel program - The SDAccel.ini has been replaced by the xrt.ini file **SDx 2019** ( [https://www.xilinx.com/support/documentation/sw_manual…