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# Host Env
* cocotb version = 1.6.0,
* os version = centos7.6 x86_64,
* simulator and version = Questa Sim-64 vsim 10.7c,
* Python version = 3.6.8
## Step 1
[axil_ram](https://github.com/…
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Hi,
I have experience in Python, but I am new to Verilog and I am having some problems trying to create a working test. The problem I am having is around the issue of the toplevel. As I didnt find …
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I'm using cocotb 1.6.1 on windows 10 (x64) with Anaconda (Python 3.9.7) + QuestaSim as simulator. (I'm a newbie)
I'm trying to add `-svinputport=net` as an argument for the vlog command but adding …
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Sorry for opening many tickets recently, I'm trying to move all our test cases to cocotb-test. I hope you don't mind.
For mixed language simulations, sometimes different compiler arguments are need…
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Might be OOM or stack overflow. found by fuzzer. Crasher attached. Backtrace:
Unhandled exception:
@ 0x56493ca85c62 GoogleTerminateHandler()
@ 0x56493cb4e028 third_party/llvm/ll…
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The following things need to be done to complete the Qt5 migration. The Qt5 port is located here: https://github.com/ra3xdh/qucs_s/tree/qt5
- [x] Import Qt3 compatibility classes from Qt4 source; …
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Can import the source code of Verilog and generate graphic interactive simulation function
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I get errors after running Full Testbench. As you can see the below picture, after configuration phase the input ports seems like OK in GPIO pad but the output ports are settled to unknown. So the tes…
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I am trying to use this in my Project, where Verilog code has some included files, while running Xcelium we will mention the directories as +incdir+.
But How to provide the directory path for c…
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I really don't care whether treadle or verilator is used as my simulation backend. The only thing I care about is accuracy and speed. Assuming they are both accurate, then the only concern is speed. T…