-
Let's discuss my approach to random math in Cryptonight. You can post test results in this thread: https://github.com/SChernykh/CryptonightR/issues/2
Basic algorithm description:
- https://github.…
-
Currently, after installing you need to set the following environment values;
```
export PATH="$INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
source "$INSTALL_DIR/$FPGA_FAM/conda/etc/…
-
This is a tracking issue to compile the work of footprints for Xilinix BGAs.
https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf
**1. Artix-7**
- [x] Script P…
-
I wonder if nextpnr has a way to put constraints on I/O-timing. In Quartus, there's set_input_delay and set_output_delay (I found http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/ to b…
-
Hi,
I would like to use Xilinx DPU to accelerate RNNs/LSTMs on a ZynqMP Platform, preferably ZCU102 or ZCU104. As far as I know the DPU-TRD dosn't support those layers. But I have found DPU-RNN (ht…
-
https://vvviy.github.io/2018/09/12/nv_small-FPGA-Mapping-Workflow-I/
Keep self busy.
VVViy updated
2 years ago
-
The documentation does not appear to include instructions for installation of SweetAda; a "getting started" section would be very helpful.
For example, does one simply download and unpack the toolc…
-
Hi ,
i 'm try to enable FPGA Spartan 6 SP605 with FT601 using the link (https://github.com/ufrisk/pcileech-fpga/tree/master/sp605_ft601)
while i'm trying to flash the FPGA card.i could not make …
-
Not sure where else to put this, but I was actually interested in this exact same concept, and there isn't really anything on the 'net about this. Do you have any interest in working on this project?
…
-
This issue concerns the branch to resolve issue 196: https://github.com/Xilinx/ACCL/tree/196-reduceallreduce-issues-on-cyt_rdma
Gather sometimes switches up the output of the first rank and the sec…