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I found a case where Verilator's simulation is incorrect. The bug manifests when a particular circuit uses a wire's value three times, but not if it is only used twice.
The attached [cse-bug.tar.g…
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BUFFERSIZE does not exist and causes compile errors when you run the makefile
https://github.com/NVlabs/matchlib/blob/924afbff5e27d09043b3587f558ee82c659cb23a/hls/unittests/WHVCRouterTop/go_hls.tcl…
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I tried to build a module that reads a file and uses the value to drive outputs, and got the following error:
```
$ verilator broken.v --cc
%Error: Command Failed /usr/local/bin/verilator_bin bro…
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Author Name: **Slava B**
Original Redmine Message: 3084 from https://www.veripool.org
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Hi,
I was curious why single-bit signals are represented in verilated SystemC code as:
```VL_SIG8(…
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Author Name: **Slava B**
Original Redmine Message: 3077 from https://www.veripool.org
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Hi,
First of all, thanks for the great tool. I took a big design, written in Verilog, and converted…
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Author Name: **Joseph Shaker**
Original Redmine Issue: 1486 from https://www.veripool.org
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Hi all, I;ve used verilator for a while on Linux and have had no problems, however I wanted to s…
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I built nv_small RTL with [this guide](http://nvdla.org/hw/v2/environment_setup_guide.html#build-test-bench). I got following error and it seems like there's no vcs in my test environment.
```
esa@h…
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Author Name: **Julius Baxter** (@juliusbaxter)
Original Redmine Message: 3162 from https://www.veripool.org
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I want to write some functions in the same C++ file as the main() function is …
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1. git clone the vp and set up environment.
2. git clone greenlib and install, then copy findgreenlib.cmake to vp directory.
3. change python3 to python2.7
4. cmake -DCMAKE_INSTALL_PREFIX=build -DS…
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Latest CMakelists.txt uses LLVM_INSTALL_DIR rather than LLVM_BUILD_DIR but paths.sh and paths.fish in scripts have not been updated to set LLVM_INSTALL_DIR.