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I have 2 alveo U280 cards on a same host, directly connected.
Built the design using `make all DEVICE=xilinx_u280_xdma_201920_3 INTERFACE=3 DESIGN=benchmark`
Here's what I was trying to run:
```
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I am trying to build IP for network interface that is in the github(https://github.com/Xilinx/xup_vitis_network_example) for ALVEO U280 FPGA. I am running make file provided in the code.
make all D…
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I am trying to run 'basic' design of xup_vitis_network_ example IP through C++ host code (from branch host_xrt).
./rx vnx_basic_if0.xclbin
I am getting following error:
Device created: xili…
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### Run Time Issues
_The system environment is at the bottom._
## Problem Description:
I have 2 alveo U280 cards on a same host, directly connected.
Built the design using `make all DEVICE=x…
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I am trying to build IP for network interface that is in the github(https://github.com/Xilinx/xup_vitis_network_example) for ALVEO U280 FPGA. I am running make file provided in the code.
make all …
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For the Xilinx Alveo U280 board the memory tests are still only partly passing. Here is a scenario that I hope will be helpful.
I boot LiteX onto the board and write a bunch of zeros to the DDR4 me…
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From @msdisme :+1:
what is the form factor of those DPUs (PCIe x1, x4, x8, x16, x32?, v3 or v4?) Thickness of the card too, is it going to take more than 1 slot for cooling? Talking about cooling, a…
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Hi, I found a bug with `setup/alveo/setup.sh`. When following instruction to setup environment (for Alveo U50) after entering docker container, I notice that the last 2 env variables are wrong:
```sh…
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When I run make synthesis. It gets errors
![0001dab6cf688535210992250d76416](https://user-images.githubusercontent.com/93361566/158084238-319132d7-b964-48ef-a8d6-aac93651b9d4.png)
'bitwidth' attrib…
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Hi,
I am following [quick start for alveo](https://github.com/Xilinx/Vitis-AI/blob/master/tools/Vitis-AI-Library/README.md#quick-start-for-alveo) for running the example models and when I try to ru…