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The verilog logic relies on unsafe information like 'primitive_type' ('unary', 'binary', 'mux', 'other') that were originally just a way to efficiently generate verilog primitives. This should be chan…
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Keyi @Kuree is running CGRA pnr test and need the unified buffer to be generated. When I set `use_ubuffer=true`, it break your coreHLS codegen. Do you have a quick fix for this? @dillonhuff
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Profiling -Jeff
cansel -Lenny
mem-hack -Lenny
master_Freeze_8_21_18 -Ross
mnr -Ross
object -Ross
Simcheck -Ross
Devtest -Ross
virtualtg -Ross
448b-freeze -Ross
typelang -Ross
@leonardt,…
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- [ ] Apply .clang-format to all files
- [ ] Replace all headers with #pragma once
- [ ] (tentative) Move Simulator into separate repo
- [ ] Update build-system
- [ ] Use external projects direc…
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The following generated verilog has two bugs in generation:
1) VTop does not have a clk signal (line 568 of uncorrected)
2) Invalid verilog syntax (line 48 of uncorrected)
[uncorrected is "assig…
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I'd like to add some logging infrastructure so we can more easily develop/debug with something more flexible than using `std::cout` and comments.
My initial search reveals: https://github.com/gabim…
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Update the mantle primitives to use the `Declare` pattern that was started in https://github.com/phanrahan/mantle/blob/master/mantle/primitives/arith.py
This ensures that all primitives across diff…
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nextpnr reports critical path with Verilog source code line number. https://github.com/YosysHQ/nextpnr/pull/494
Is it possible to get Magma source code file name and line number from the Verilog sour…