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When I use the latest [marcos_extras](https://github.com/vnegnev/marcos_extras) such as branch [vn/mimo](https://github.com/vnegnev/marcos_extras/tree/vn/mimo)
or a self compiled FPGA bit file, [vn/…
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Hi,
I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in my machine. I was able to generate the bitstrea…
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From: [James Wharrie](https://www.linkedin.com/in/james-wharrie-03b96379/) on [LinkedIn ](https://www.linkedin.com/groups/66949/66949-6340416723170226178)
A very useful utility as I lost count of t…
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I was wondering what learning resources are available regarding the programming of the iCE40HX4K in the Alhambra-II using the VHDL language rather than Verilog/SystemVerilog. The reasoning for this is…
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I'm unsure how this exact feature could be called - i've seen it's called "flickerblend" in Lynx core.
To start - there's a Samurai Shodown game, that shadows implementation (drawing black sprite at …
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Hi, and thanks for this cool project. I have build the hardware and programmed the MCU und FPGA. Everything worked fine until the test procedure.
I got 0.00 MB/s at the transfer speed, and i have no…
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I wasn't sure how else to communicate with you, as I couldn't find an email address.
Have you seen the project fpgalink. It has utitlies and drivers for easily communicating with many different board…
ghost updated
11 years ago
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Hi Hugh,
[MXNET](https://github.com/dmlc/mxnet) is an established Deep Learning framework with tonnes of powerful features and wide range of programming language support. With my recent experience …
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Hi,
I struggled with this strange issue for a couple of days and finally found out that,
for some weird reason, configuration failed (DONE pin on the FPGA not coming high)
when I tried to load a L…
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I find having affordable and easily accessible dev kits lowers the bar to entry which is probably why projects like speeduino and rusefi have taken off.
For dev hardware I've chosen a ColorLight 5…