-
### What would this enhancement be for?
Hammer
### Describe your enhancement suggestion in more detail
allow for parameter override to have presets in the fgd, but still be overridable, this makes …
-
/area autoscale
## Describe the feature
I would like to request to appropriately handle the Pods with [shcedulingGates](https://kubernetes.io/docs/concepts/scheduling-eviction/pod-scheduling-r…
-
![image.png](https://raw.githubusercontent.com/e0426051/pe/main/files/c86a046d-4323-494e-93fc-891362f12f8f.png)
Below the "OUT" in the diagram, there is a vertical line signalling the channeling of b…
-
I would like a sub menu on the logic gate that lets you select the type before putting it down. It'll make putting lots of gates down easier.
-
![Screenshot_2022-07-20-08-58-15-62_33e07244786ec8aea651eea65ad70e5e.jpg](https://user-images.githubusercontent.com/87870432/179881489-4942ed80-bad2-4e2c-acbb-498fa9e3365e.jpg)
Hello@Proto-App
in thi…
-
Hello,
I'm using Orca Slicer printing a simple dual color with just one material swap, so no purge tower.
I added this in Machine start Gcode `MMU_START_SETUP INITIAL_TOOL={initial_tool} REFERENCED_…
-
Hi Lauge,
I was working on your simulator and due to some reason this happened
![Screenshot (57)](https://user-images.githubusercontent.com/102138892/228879446-2f09b1a4-636d-4fd6-9181-3a33f9a61e…
-
There is no support for removing or editing additional gates, this makes it rather difficult to manage larger logic gate configurations.
[original: nus-cs2113-AY2021S1/pe-interim#17]
-
### Short Description of the issue:
Logic Gate Inconsistency
### Steps to reproduce the issue:
Make any logic gate circuit that is dependent on which signal gets there first, and then add som…
-
Can it support Binary logic diagrams as well? like AND, OR, XOR gates?
Also with advancement of AI tools, i guess its simulator would be also feasible though it may be fall under new project instea…