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To quote the README.md of this repository, and the text on the Sparkfun website:
'What sets the RED-V RedBoard apart from the rest is the completely open-source approach from hardware to ISA. That …
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When the attached is compiled as follows, it generates an ICE:
during GIMPLE pass: pcom
isp_flasher.c: In function 'main':
isp_flasher.c:125:5: internal compiler error: tree check: expected ssa_nam…
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**Type of issue**: bug report
**Impact**: FPGA Building
**Other information**
lore@Helium:~/src/rocket-chip/vsim$ make verilog CONFIG=DefaultFPGAConfig
mkdir -p /home/lore/src/rocket-ch…
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# RISC-V from scratch 1: Introduction, toolchain setup, and hello world!
A post that discusses what RISC-V is and why it's important, teaches readers how to install the GNU RISC-V toolchain, and walk…
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Please add support for BL602/BL604 made by BouffaloLab
> The BL602 is a general purpose microcontroller based on the “SiFive E24 Core” RISC-V processor.
Notice that it's only _based on_ the SiFi…
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I want to connect an IP core with AXI4-Lite in SiFive Freedom Unleashed (using branch bump-stuff) on the VCU118. For simplicity I test with the Xilinx AXI GPIO.
Snippets how the GPIO IP core is con…
manox updated
2 years ago
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問問題可以用 Google Meet ---- https://meet.google.com/otw-auax-kne
或在本討論區留言
1. https://www.sifive.com/software
* 方法 1 : Download Freedom Studio
* 方法 2 : 下載 GNU Embedded Toolchain + QEMU
…
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**Type of issue**: bug report
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Run vlsi_rom_gen with python3.5 or higher, e.g., `python3.7 scripts/vlsi_rom_…
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**Describe the bug**
I tried to build MaixPy with TensorFlow Lite Micro hello world example, but fail in finding *.h in MaixPy build. I am not familiar with cmake build, does not know how to add "inc…
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I am having this issue while compiling hello.c. I tried the solution mentioned in the other issue as well. Please see the compilation results below:
**PS: I noticed that I did not have riscv-elf fo…