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I'm very interested in ghdl_ls there are however some starting hurdles that I've got to overcome.
**1. How does a project have to be setup for multiple libraries (not only work). Multiple sections?…
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Every run with this action will produce some deprecation warnings. It needs to switch to node 16: [See](https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16…
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Pre-processing:
- [x] autolink "http://"
- [ ] autolink model entities, namespaces, signature etc
- [ ] autolink pages and sections
Checking:
- [ ] spell checker
- [ ] style: indent, uppercase at the…
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Here is the log：
[TMAKE]: building nv_small in spec/odif
[TMAKE]: building nv_small in vmod/vlibs
[TMAKE]: building nv_small in vmod/include
[TMAKE]: building nv_small in vmod/rams/model
[T…
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The Bluespec compiler emits Verilog which makes **[Yosys](https://github.com/yosyshq/yosys)** somewhat unhappy:
```
1.3. Executing Verilog-2005 frontend: /tmp/yosys-bsv-v-QxaOnJ/keccak.v
Parsing …
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DCD Synopsys on stm32f4/f7 and esp32s2 this mark is not enabled but the interrupt fired anyway. Enabled it at first cause issue with setup (possibly due to data not ready).
**Original discussion**:…
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## Observed Behavior
I simulated the simple system example using VCS, following the guide in https://github.com/lowRISC/ibex/blob/master/examples/simple_system/README.md
I build the simulati…
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Our current query interface is synchronous which was unfortunate oversight on my end since clearly we can't block while fetching data over the wire.
@relves proposed changes in #22 that was fixing …
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hello,
Just a query on is there any possible way for having a "**runset**" for ICV and other files needed for physical layouting and verification on synopsys tools.
can it be generated?
or is …
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- [현대자동차](https://www.hyundai.com/kr/ko/e)
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