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Hi,
it seems that vivado xsim doesn't support generating xilinx ip for simulation.
It is supported for synthesis
Is it a planned feature?
If not I would be willing to help implementing it.
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The downloads page that the doc points to no longer exists.
https://cfu-playground.readthedocs.io/en/latest/vivado-install.html
points to
https://www.xilinx.com/support/download/index.html/c…
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Hi,
I have a Zybo z7-10 and a Zedboard and use Vivado 2018.3 and SDK 2018.3 (due to the previous developers of the project).
I'm trying to run the xtrafgen_master_streaming_example.c of the Traf…
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I got that compilation error while trying to build chaidnn using SDSoC v2018.3
Creating Vivado project and starting FPGA synthesis.
What could be the reason of that error ?
WARNING: [VPL…
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Ran make nexys4_ddr_rocket with Vivado 2018.3
and have ERRORs
any hint ?
WARNING: [filemgmt 56-315] Source scanning failed during design analysis. To get more details run synthesis or simulation …
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**Description**
I am trying to compile Xilinx vendor library to GHDL. The pass to the library sources on my machine is : C:\Xilinx\Vivado\2020.1\data\vhdl\src\std_2008
env.vhd
standard.vhd
textio…
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I've been trying to simulate my design that includes Xilinx Aurora 8B/10B core. I find the alternatives (ModelSim Started, Xilinx XSIM) either very slow or cumbersome to use in script mode, so I'm try…
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Using ":" as separator create some issue for windows absolute path utilization .
test case:
--include unisim:%XILINX_VIVADO%/data/vhdl/src/unisims
expands into:
C:\Xilinx\Vivado\2019.1\data\vhd…
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**Description**
`--vendor-library=NAME` is a synth option which allows to replace any unit from `LIB_NAME` with a black box during synthesys:
https://ghdl.github.io/ghdl/using/Synthesis.html
…
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**(Approach #1)**: ghdl-0.33, vendor scripts from `'master'`
I have GHDL 0.33 (pre-build binary) on Windows, so followed [this guide](https://ghdl.github.io/ghdl/getting.html) to install Xilinx Vivad…