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Author Name: **Cheng Fei Phung**
Original Redmine Message: 2261 from https://www.veripool.org
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For verilator, anyone have experience using dump() with non-integer timestamp ?
The reason …
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Hi,I got the code and compile,but get errors as flow:
g++ -fpic -O2 -I./ -I./verilated -I../../isa_sim -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I/usr/local/systemc_2.…
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testbench.h: In constructor ‘testbench::testbench(sc_core::sc_module_name)’:
testbench_vbase.h:12:41: error: invalid new-expression of abstract class type ‘VerilatedVcdSc’
VerilatedVcdS…
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**BUG DESCRIPTION**
I had no problems with the compilation, but when I try to start a .asm test I always receive an exception at the beginning of the simulation (the same for each .asm). I didn't tri…
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followed the instruction from http://nvdla.org/vp.html#prepare-kernel-image
after this command: ./build/bin/aarch64_toplevel -c conf/aarch64_nvdla.lua
SystemC 2.3.0-ASI --- Jun 19 201…
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Author Name: **Oleg Rodionov**
Original Redmine Message: 3087 from https://www.veripool.org
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In my vcs simulation model, for certain, simulation content, I see majority of simulation time…
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Sorry bad English
game:
マッチング結婚~アプリで見つける最高の花嫁~
https://vndb.org/v25922
H CODE: /HQ4@63610:matchingm.exe
This not happens only with this game, this happens with all game shat I tried it.
I…
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In preparation for a public review we need to refresh the examples' PowerPoint presentations. This includes the following:
- Update any outdated terminology - e.g. replace "accessor" with "handle"
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Author Name: **Slava B**
Original Redmine Message: 3033 from https://www.veripool.org
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Hello,
I was asked to convert a big Verilog project to SystemC. I'm a novice in Verilog and cannot …
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When attempting to run the unmodified sample at
https://github.com/dart-lang/samples/blob/master/ffi/system-command/macos.dart
I get the following error:
```
➜ dart_ffi: $ dart macos.dart
Crash…