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ultraembedded
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core_sdram_axi4
SDRAM controller with AXI4 interface
GNU General Public License v3.0
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166MHz operation
#4
AnttiLukats
opened
1 year ago
0
VCD files are not generated
#3
ABADY1000
closed
1 year ago
0
port mapping the top module with AXI ip
#2
Madesh12
closed
4 years ago
8
some error has disppear when run tb/make
#1
langrange-L
closed
5 years ago
1