-
We are running `make` under `..../corundum/fpga/mqnic/AU50/fpga_100g`, the board package for au50 is installed and our vivado version is 2022.2, whith SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022,…
-
### Severity
Minor
### Versions
20.6.0, 18.21.0
### Components/Modules
core
### Operating Environment
Debian Bookworm based Docker container
### Frequency of Occurrence
Constant
### Issue De…
TJNII updated
3 weeks ago
-
The application_fpga currently meets 24 MHz after P&R, but is clocked at 18 MHz. We should be able to increase the clock to ~22 MHz and still have good timing margin. This would improve performance wi…
-
The following is generated from the description below:-
![image](https://github.com/plantuml/plantuml/assets/8818025/68b75cca-10c4-4a1a-96b1-e60b23746cf7)
```txt
@startuml
analog "Days more t…
-
### Which jobs are flaking?
pull-kubernetes-integration
### Which tests are flaking?
It looks like random tests are failing, for example:
- TestUnReserveReservePlugins/The_Reserve_plugins_succee…
-
Find best timing according to HD44780U's datasheet Timing Characteristics.
And figure out formulae for easier porting to other MCUs.
-
### Problem
I work in Python, Julia and APL, often comparing the performance of the kernels. It would be very helpful if there were a
kernel-agnostic magic for reporting the elapsed, cp…
-
## Problem
[Server-Timing](https://postgrest.org/en/latest/references/observability.html#server-timing-header) currently conflates the pool [checkout time](https://stackoverflow.com/questions/55316…
-
https://github.com/Lzhikai/SIBOOR-Voron-Trident-June/blob/main/SIBOOR_Trident_%5BJUNE_2024%5D_BOM.md
![image](https://github.com/Lzhikai/SIBOOR-Voron-Trident-June/assets/6583561/ea48692e-ffac-421e-8e…
-
I have a question, at line 173 of StreamMapNet.py:
#Backbone
_bev_feats = self.backbone(img, img_metas=img_metas, points=points)
It seems that the prev_bev parameter (previous bev featues) is not g…