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Write "DO NOT HOTPLUG" next to the EEM connectors schematic/pcb
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Results of DDR verification
 using a [banner](https://github.co…
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In followup to [meeting on 2/18](https://github.com/sinara-hw/sinara/wiki/Sayma-v2-meeting-number-6) there was discussion about FPGA for a future roll of Metlino.
> 8. Discuss Metlino FPGA. Can we…
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_From @marmeladapk on [2018-01-31 09:53](https://github.com/sinara-hw/sinara/issues/499)_
- [ ] Rotate SATA connector
- [ ] Have I2C and UART signals in the same bank (each of them)
- [ ] Switc…
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# Bug Report
## One-Line Summary
If a gateware target has no moninj probes (for example, consists only of an SUServo) the gateware build errors-out.
## Issue Details
### Steps to Rep…
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`msgpack-python` dependency is depracated and leads to coillisions when used with recent msgpack in Nix.
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# Bug Report
## One-Line Summary
On kernel, there is no convenient way of getting the absolute value of a number.
## Issue Details
### Steps to Reproduce
1. Save one of the belo…
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I'd like to aim to use upconverters with inbuilt LO PLLs. The thinking here is that it's highly desirable to have a LO PLL on the EEM, rather than relying on an external LO. Generating the LO with a P…
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# Question
## Category: Gateware/Coredevices
## Description
**Is there any sort of UART/USART driver in ARTIQ?** I've looked through documentation and coredevices, but can't see anything simi…