sinara-hw Metlino issues

sinara-hw / Metlino

microTCA carrier hub (MCH) Tongue 3 FPGA module with HVDCI and SFP

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issues

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route Fabric E

#73 gkasprow opened 3 years ago
6
Possible typo in I2C mux address

#72 HarryMakes closed 2 years ago
2
Add LVDS variant

#71 marmeladapk closed 2 years ago
3
No P3V3 MP on Metlino #105

#70 marmeladapk closed 4 years ago
7
photos of Metlino

#69 jbqubit closed 4 years ago
7
Si5324 I2C low level is too high

#68 marmeladapk closed 4 years ago
6
SFP/USB plug collision

#67 sbourdeauducq opened 4 years ago
9
Components too close to the board edge

#66 kaolpr closed 2 years ago
2
Too high heatsink

#65 kaolpr opened 4 years ago
4
front panel

#64 jbqubit opened 4 years ago
3
SDRAM REFIN is missing ground connection

#63 marmeladapk closed 2 years ago
3
Flash memory

#62 marmeladapk closed 2 years ago
1
Si549 populated with LVDS not CMOS

#61 jbqubit closed 4 years ago
9
manufacturing and testing status

#60 jbqubit opened 4 years ago
14
Si analysis

#59 gkasprow closed 5 years ago
7
PI analysis after optimization

#58 gkasprow closed 5 years ago
8
Schematic cosmetics

#57 marmeladapk closed 5 years ago
1
Power integrity check

#56 marmeladapk closed 5 years ago
0
Polygons

#55 marmeladapk closed 5 years ago
0
Thermal via solder mask tenting

#54 marmeladapk closed 5 years ago
1
Silkscreen

#53 marmeladapk closed 5 years ago
1
Two holes close to each other

#52 marmeladapk closed 5 years ago
3
Pad B17 goes beyond PCB edge

#51 marmeladapk closed 5 years ago
1
Missing stackup table

#50 marmeladapk closed 5 years ago
1
Rear_SMA_CLK_IN should be 50R

#49 marmeladapk closed 5 years ago
0
No additional vias when changing layers

#48 marmeladapk closed 5 years ago
0
P11 plane

#47 marmeladapk closed 5 years ago
1
Can some types of vias be removed?

#46 marmeladapk closed 5 years ago
1
OutputJob

#45 marmeladapk closed 5 years ago
1
PCB and schematics are not synchronized

#44 marmeladapk closed 5 years ago
2
PCB DRC

#43 marmeladapk closed 5 years ago
1
Mismatched port names

#42 marmeladapk closed 5 years ago
1
Missing file

#41 marmeladapk closed 5 years ago
1
testpoints

#40 gkasprow closed 5 years ago
0
position of GC pins on VHDCI connector

#39 sbourdeauducq closed 5 years ago
1
stop calling everything "WR"

#38 sbourdeauducq closed 5 years ago
6
external clocking

#37 sbourdeauducq closed 5 years ago
19
Si5325 typo

#36 sbourdeauducq closed 5 years ago
1
CLK_200MHz must reach Quad 228

#35 sbourdeauducq closed 5 years ago
1
SDRAM64_CLK_N not connected to VTT64

#34 kaolpr closed 5 years ago
1
Many differential signals do not have differential directive

#33 marmeladapk closed 5 years ago
0
Add 3V3_CLK enable control

#32 marmeladapk closed 5 years ago
0
Metlino MMC

#31 gkasprow closed 5 years ago
4
RGMII_MDIO multiple net names

#30 marmeladapk closed 5 years ago
1
Schematic cosmetics

#29 marmeladapk closed 5 years ago
1
DNP check

#28 marmeladapk closed 5 years ago
4
Beef up 5V USB to 3.3V LDO

#27 marmeladapk closed 5 years ago
0
Remove R344/R343 resistors

#26 atcher0 closed 5 years ago
2
WR_REF_CLK clock should have AC coupling capacitors

#25 atcher0 closed 5 years ago
0
IC12 missing ground

#24 marmeladapk closed 5 years ago
0