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# Question
## Category: Gateware/Coredevices
## Description
**Is there any sort of UART/USART driver in ARTIQ?** I've looked through documentation and coredevices, but can't see anything simi…
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# Bug Report
## One-Line Summary
Issues with references when allocating multi-dimensional array on core.
## Issue Details
### Steps to Reproduce
Sample code:
```python
import artiq
f…
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I'm not sure is this is actually related to nMigen or if this is purely a nextpnr bug, but HeavyX simplesoc_ecp5 no longer works after attempting to use ``nmigen.build``.
I had to update Yosys and ne…
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We need some way to define platform connectors, like in oMigen. But in oMigen this feature was somewhat inconvenient. I would like to collect feedback from everyone who used it so that the nMigen one …
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If a bigger/better heat sink can not keep the die temperature low enough in typical air flow conditions (I don't want to rely on forced airflow for these crates, most people don't seem to bother with …
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@gkasprow for the stub ARTIQ port we need the FPGA pinout
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Graphics placed in schematics are linked to local content and can not be opened.
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# Bug Report
## One-Line Summary
Async co-routines have different reader limits. Related: #285
## Issue Details
### Steps to Reproduce
AsyncioClient:
https://github.com/m-labs/artiq/…
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**Issue by [mithro](https://github.com/mithro)**
_Thursday Jun 06, 2019 at 23:26 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/92_
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How do you suggest adding support for us…
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c.f. https://github.com/m-labs/artiq/issues/1065
* VCCINT setpoint too low
* VCCINT unstable and dropping under load
Note that we envision an increased FPGA consumption as more ARTIQ/SAWG featu…