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Currently it gives the general parser help message. It should give the help message for the 'gen' subparser.
(Hi Olof. I'm mostly adding this to remind myself to look at it when I'm not at work. …
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I am using this command to generate vivado project using FUSESOC:
`fusesoc --cores-root $OPTIMSOC_SRC/examples/fpga/vcu108/compute_tile build optimsoc:examples:compute_tile_vcu108 --NUM_CORES 2`
…
SRQ91 updated
5 years ago
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I'm trying to think about how to deal with generators whose parameters need to be calculated by a different generator. This is necessary to mix different verilog-generating languages, and also to be …
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I am trying to get the file structure for single tile quad core system of OpTiMSoC. The make of OpTiMSoC runs fine but generates only single core single tile vivado project in the objdir/examples/fpga…
SRQ91 updated
5 years ago
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The Core file parser causes a 'list index out of range' error when encountering an empty first line.
.split()[0] assumes a non-empty first line.
```python
class Core(object):
def __new__(c…
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I was just experimenting with FuseSoC's ability to pass arguments to the edalize backends for overriding top level parameters / generics. It appears that at present only verilog params and defines wor…
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In the `fusesoc-cores` project we have mor1kx version [v5.0](https://github.com/fusesoc/fusesoc-cores/tree/master/mor1kx)*
We should be synced with @olofk and making tags.
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Currently I am compiling for the VCU108 by modifying the build.py and replacing nexysddr with vcu108. This works fine but I am wondering if there is a more refined method already implemented for this?
SRQ91 updated
5 years ago
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The --elab-run command of ghdl requires the analyze-options to work correctly. So line 54 in ghdl.py should be changed to
`ghdl --elab-run $(ANALYZE_OPTIONS) $(STD) $(TOPLEVEL) $(RUN_OPTIONS) $(EXT…
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make fails in FPGA Build process of nexys4ddr with the following Log-Messages:
WARNING: Parse error. Ignoring file /optimsoc-sources/examples/fpga/nexys4ddr/compute_tile/compute_tile_nexys4ddr.cor…