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Current Version commit b3bdff1
I am trying to use the stitched IP approach for a non-PYNQ FPGA board. I can successfully output the stitched IP design but when IP-XACT is generated it doesn't have …
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`tapacc` currently still looks for system include paths:
```
/usr/include/c++/v1
/usr/local/include
/usr/include/x86_64-linux-gnu
/usr/include
```
In particular, the `/usr/include/c++/v1` i…
Blaok updated
1 month ago
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![image](https://user-images.githubusercontent.com/64191224/186342357-af479df4-6bf9-46fa-8a45-a86534511c24.png)
Recently, this problem has occurred in all runs
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The link for the vitis-workspace.tcl file (https://xilinx.github.io/Embedded-Design-Tutorials/docs/2022.2/build/html/docs/Vitis-Embedded-Software-Debugging/docs/3-debugging-linux-applications/script/V…
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I have questions about Vitis Model Composer.
- Is Sysgen rebranded to Vitis Model Composer, or are they 2 different products?
- Will HDL-Coder work with Vitis Model Composer / is it necessary?
- …
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I followed the guide to build this project for target `vck190_fmcp1`. Running: `make petalinux TARGET=vck190_fmcp1` works just fine, but when I program the board, the boot process stalls early on with…
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Hello Pavel,
I start in FPGA Programming with Vivado on the red-pitaya and I would like to realize a simple digital low-pass filter with the FIR Compiler IP.
To test, i connect an adjustable sine ge…
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Here I'm using the zcu102 board.
I imported the vivado project containing DPU into the petalinux project, and generated the corresponding image through the petalinux tool, and successfully ran the d…
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## 🐛 Bug
The Android app crashes when I click on the 'chat' icon next to the model's name after flashing "Initialize..." for a second over the chatting interface.
## To Reproduce
Steps to rep…
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I deployed the DPU using my own board, and in order to debug, I opened all the DEBUG in the vart library. Then, I executed the resnet50 inference process in the app and encountered the following error…