-
I'm not able to compile the file "sim_waveform.vhdl" using Vivado (Version 2015.2).
I get the following errors:
```
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/s…
-
When I run the gqesort demo in /Vitis_Libraries/database/L2/demos/gqeSort/,I got this:
[XRT] ERROR: std::bad_alloc
Create Device buf_in 0 Failed!
-
Hi - Not really an issue, but I just want to start a discussion. I was wondering if there are any plans to move the linux-kernels/uboot repos to 2020.1? the fpga manage has matured so loading bitstrea…
-
hello,i don't know how to run the python script ,could you help me?
-
Currently, some bare-metal tests have issues running on the Xilinx Virtex Utralscale+ board. We have to debug these issues using Vivado's post-synth simulation and add compatibility tests to our regre…
-
When I run with cli_test hs2, there are some error like below:
`**Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
In…
-
Hi Jeremy,
I'm trying to DMA very large buffers (512M byte if I can) into memory. I seem to run into a memory problem for sg_alloc_table if I try to create a DMA buffer > 1Mbyte. I believe I just hav…
-
Im trying to reproduce some performance numbers mentioned in HCL paper on AWS F1.
```shell
===>The following messages were generated while performing high-level synthesis for kernel: default_func…
-
I need to program some (older) FPGAs that are not included in the device list. I tried adding the devices to `device_list.txt` and I was able to detect it, but I was not able to assign the `-X paralle…
-
When Ethernet full-duplex communication is performed (especially at high rates - over 1Gb Ethernet), it is noticed that Tx side of communication becomes the dominant one and completely "kills" the Rx …