VLSI-EDA PoC issues - Githubissues

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

https://tu-dresden.de/ing/informatik/ti/vlsi

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issues

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Vivado configuration fails

#73 poneill1001 opened 10 months ago
1
Please update link to OSVVM

#72 JimLewis opened 1 year ago
0
CYCLONE II FPGA with TM1638 in VHDL code

#71 paskalthelordoffpga opened 1 year ago
3
Failed to configure

#70 albydnc opened 1 year ago
3
Is this library being maintained?

#69 hcommin opened 2 years ago
1
GHDL VHDL -> Yosys code for BLOCKRAM (used as ROM)

#68 PPlinux opened 2 years ago
0
Error during configuration

#67 mbieker opened 3 years ago
2
non-pipeline fp divider modules testbench

#66 Divya2030 closed 3 years ago
0
Fixed single-bit synchronizer interface.

#65 preusser closed 4 years ago
0
Add license scan report and status

#64 fossabot closed 4 years ago
0
"misc_strobegenerator" is missing

#63 rhentges opened 5 years ago
0
configuration problem

#62 sasamy1 opened 5 years ago
6
Overloaded ite for signed datatype

#61 FranzForstmayr closed 5 years ago
2
Fixed Sphinx output

#60 FranzForstmayr closed 5 years ago
0
Corrected typo

#59 japm48 closed 6 years ago
0
Submodules are not up-to-date

#58 FranzForstmayr opened 6 years ago
7
dockerize tests

#57 eine closed 2 years ago
1
fifo_dc_got.vhdl is missing

#56 rhentges opened 6 years ago
0
Updated a few READMEs in src

#55 cjchin closed 6 years ago
0
What is the meaning of namespace and sub namespaces?

#54 cjchin closed 6 years ago
2
Update __init__.py

#53 cjchin closed 6 years ago
3
Update grc.setup.sh

#52 cjchin closed 6 years ago
0
Update README.md

#51 cjchin closed 6 years ago
0
Pre-Compile Option for GHDL

#50 FranzForstmayr closed 3 years ago
1
configuration crashes at Intel Modelsim setup

#49 jobermueller opened 6 years ago
5
Error for string.vhdl - Value := resize(slv, Value'length);

#48 bhamadicharef opened 6 years ago
8
docs: wrong github url in git in quick start guide

#47 Martoni closed 7 years ago
1
News is in Latin on readthedocs front page.

#46 GadgetSteve closed 7 years ago
2
Doc: Document the change log from v0.0.0 until now

#45 Paebbels opened 7 years ago
0
PyInfra: Add tool support for Aldec Riviera-PRO

#44 Paebbels opened 7 years ago
0
Rewrite testbenches and simulation packages for VHDL-2008 only.

#43 Paebbels opened 7 years ago
0
Doc: Document installed Sphinx extensions, usable syntax, modifications

#42 Paebbels opened 7 years ago
0
Doc: Document Python dependencies in the Quick Start Guide

#41 Paebbels opened 7 years ago
0
PyInfra: Add tool support for Xilinx Vivado IP Catalog

#40 Paebbels opened 7 years ago
0
PyInfra: Add tool support for Synopsys Synplify Pro

#39 Paebbels opened 7 years ago
2
PyInfra: Add tool support for Mentor Graphics Precision-RTL

#38 Paebbels opened 7 years ago
0
PyInfra: Add tool support for Cadence Incisive

#37 Paebbels opened 7 years ago
0
PyInfra: Calculate compile order of VHDL files.

#36 Paebbels opened 7 years ago
0
PyInfra: Provide a PowerShell drive

#35 Paebbels opened 7 years ago
0
PyInfra: Auto completion for PowerShell

#34 Paebbels opened 7 years ago
0
PyInfra: Auto completion for Bash

#33 Paebbels closed 7 years ago
1
PyInfra: A PoC reconfiguration should create a save/backup file of 'config.private.ini'.

#32 Paebbels closed 7 years ago
1
Implement wrapper for DDR3 memory controller on Xilinx KC705 board

#31 mzabeltud opened 7 years ago
1
Provide access to device temperature of IP core "io_FanControl"

#30 mzabeltud opened 7 years ago
0
Implement infrastructure tests for the Windows platform by using Appveyor.

#29 Paebbels closed 7 years ago
1
Multiple Examples in the Documentation are the same

#28 befedo closed 7 years ago
5
Create a 'reproducer' command to assemble all needed simulation files for a bug reporting

#27 Paebbels opened 7 years ago
0
Downloading: The zip files provided by GitHub doesn't contain submodule files.

#26 Paebbels opened 7 years ago
0
Document vendor tool specific project settings.

#25 Paebbels opened 7 years ago
0
Silence modelsim warnings for physical.vhdl

#24 olofk closed 7 years ago
4