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VLSI-EDA
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PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
https://tu-dresden.de/ing/informatik/ti/vlsi
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Rework README.md in PoCRoot
#23
Paebbels
closed
7 years ago
1
Delete GitHub wiki contents
#22
Paebbels
closed
8 years ago
1
fixed outdated function call
#21
krabo0om
closed
8 years ago
0
added the ICAP
#20
krabo0om
closed
8 years ago
3
Issue synthesizing uart_bclk.vhdl
#19
albertschulz
closed
8 years ago
3
Use correct initial/reset vector length
#18
albertschulz
closed
8 years ago
2
Get release branch to pass Travis build again.
#17
preusser
closed
8 years ago
1
PyInfra: Incremental Modular Configuration
#16
preusser
closed
8 years ago
1
PyInfra: Don't rmdir the working directory in /temp
#15
Paebbels
closed
8 years ago
1
PyInfra: Error reporting from *.files and *.rules file parser
#14
Paebbels
opened
8 years ago
0
PyInfra: Create my_project.vhdl after configuration
#13
Paebbels
opened
8 years ago
0
PyInfra: IP Core import into vendor tools
#12
Paebbels
opened
8 years ago
0
PyInfra: Generate better help pages for the command line interface
#11
Paebbels
opened
8 years ago
1
Sphinx Documentation
#10
Paebbels
closed
7 years ago
4
Release
#9
Paebbels
closed
8 years ago
1
Unable to compile sim_waveform.vhdl
#8
albertschulz
opened
8 years ago
2
Travis-CI integration
#7
Paebbels
closed
8 years ago
0
Gitter.im integration
#6
Paebbels
closed
8 years ago
1
Landscape.io integration
#5
Paebbels
closed
8 years ago
1
Add a Gitter chat badge to README.md
#4
gitter-badger
closed
8 years ago
0
added deque and stack
#3
vossy454
closed
8 years ago
3
Add board configurations: ML506 ML507 XUPV5 VC709
#2
marzoul
closed
9 years ago
1
Fail when running testbench
#1
marzoul
closed
9 years ago
2
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