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I synthesized compute_tile with the following:
`fusesoc --cores-root $HOME/xx/optimsoc/examples/fpga/vcu108/compute_tile build optimsoc:examples:compute_tile_vcu108 --UART0_SOURCE=onboard --HOST_IF…
SRQ91 updated
5 years ago
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According to the spec `6.3 Exception Processing`. For FPU exceptions the EPCR should be set to `Address of next not executed instruction`.
This is the same as `Tick Timer`, `External Interrupt` a…
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Found when building de0_nano-multicore. The design no longer fits on the de0_nano cyclone IV. It used to be 18210 logic cells no it has increased to 46111 logic cells.
## BEFORE
```
$ fuseso…
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Analyze_options like e.g. --ieee=synopsys must also be passed to the --elab-run command because when using the mcode backend the analyze phase does not generate any object files, so all compilation i…
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Hi all,
I'd like to propose that I set up some documentation in [Sphinx](http://sphinx-doc.org/) for the project, incorporating what is there so far but making it possible to easily build HTML and PD…
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Currently the search result page shows dates like "Updated 1 month before". This should be "Updated 1 month ago".
![grafik](https://user-images.githubusercontent.com/1467123/43675606-06a139fa-97e3-…
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Hi,
when I am using icarus as the simulator everythin is fine but when I try it with questasim (--sim=modelsim) which has the same interface and commands as modelsim I got the following error:
Runn…
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@asb @GregAC @eunchan @imphil
Opening a new issue to investigate the latencies on top_earlgrey
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I think @olofk had split the hdl backends from FuseSoC into a separate package? I can't find it now however?
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Hi,
this is a request for comments for a feature I need and want to implement. The goal is to being able to generate files during the FuseSoC run. I describe the proposed extensions below:
## Fi…