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### Description
Design hardening is a process that takes a lot of time and is a very linear process. Developers who want to run experiments need to wait for the design to finish in order to read the …
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### Description
Hi, I am trying to harden a small eFPGA (4 x 4 CLB), I have used OpenFPGA to create the FPGA architecture.
This FPGA has basic modules like CLB, switching blocks, and connection bloc…
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I downloaded the OpenLane dataset via your released python client and visualized several cases, noticeable noise labels are found for almost all images, take the below figures as example (red and yell…
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What are your plans for supporting SKY90? Thanks,
/jeff
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A few days ago, I trained a model with OpenLane_300. I got a pretty evaluation result with this model. And then I trained another model with OpenLane_1000, but this model was nowhere near as good as t…
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https://github.com/proppy/tiny_user_project/blob/8f1fa45ff74e74b929b48e59237586c80f55018c/openlane/user_project_wrapper/config.tcl#L49
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### Description
I am currently trying to reharden a design for submission to GFMPW-0. I get a crash during Detailed Routing.
First of all thanks @maliberty for taking care of #1543
The reason I…
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Is this information is saying any specific issue here ? I see u_sram_2kb/din0[15] connected to mem_din_b\[15\] and this signal information is available inside guide file : 16-fastroute.guide
open…
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### Description
I've included the SRAM IP block from GF180 in a design (gf180mcu_fd_ip_sram__sram256x8m8wm1).
When running DRC on the hardened design it failed with 100x `V3.2a : min. via3 spacing …
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### Description
When running a flow interactively on the OpenLane, at the run_magic_spice_export stage, I have faced an error like;
[ERROR]: There are illegal overlaps (e.g., routes over obstr…