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Hi,
I have an issue with the VCU108 and the FX3. Generally, OSD works, but once I start initializing the memory I have memory losses.
Steps to reproduce:
- The issue is on the current master (c…
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Currently fusesoc copies all input source files to build/XXX/src and runs the build from there. That's a suitable behavior for fully automated builds. However, during the development phase, I'm have a…
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Currently fusesoc is pretty much centered around building a synthesis or a simulation. I've recently come across the need to also support linting with different tools, such as Verilator (using --lint-…
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I'm looking into using fusesoc for dependency management without taking advantage of the simulation or image generation features yet.
I didn't see an easy to way to get fusesoc just to spit out a s…
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Hi Clifford,
I'd like to be able to call SymbiYosys from FuseSoC as a backend. My rationale is that I already have all my Verilog files and whatnot enumerated in the FuseSoC cores file, and I don't…
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Verilator pipes the linker output through `c++filt`, so that the return code is not the linker error, but the `c++filt` return code. Maybe we can handle it here, but I suppose the proper way is in ver…
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What changes needed to use this for an Actel ProASIC3? Which modules need customization?
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We got the following report from a user of OpTiMSoC
STR:
```sh
. ~/src/optimsoc/objdir/dist/optimsoc-environment.sh
. /opt/optimsoc/setup_prebuilt.sh
module load xilinx/vivado/2017.4
fusesoc…
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From previous testings, I have a core file with a [spyglass] section. fusesoc (master as of today) recognizes this section as unsupported, but still throws an exception. Either the warning should be a…
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An image is better than thousand words.
![grafik](https://user-images.githubusercontent.com/1467123/30207190-f2823828-948e-11e7-94fe-087edf599690.png)
as seen on https://www.librecores.org/olofk…