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Is the generated cache file backward compatible? i.e. if a `*.uhdm` file is generated using one version of the binary, can that same be loaded with a newer version of the binary?
I presume the answ…
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I would like to use Verilator to run RISC-V tests.
Do you know of any projects already simulating SystemVerilog projects with Verilator on GitHub CI, I could use an example to start from.
Please not…
jeras updated
2 months ago
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The core development team for VUnit does not have easy access to Cadence Incisive and Xcelium licenses which prevents us from running our acceptance tests on those simulators. To get a higher confiden…
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# Standalone Preprocessor Tool Design
## Introduction
The goal of this thread is to discuss and put the outlines of the standalone preprocessor tool.
The preprocessor tool should fully suppor…
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Use the wiki to see the list of tools:
https://fpga-mafia.github.io/fpga_mafia_wiki/docs/TFM/welcome
### Very important:
Make sure to document anything that did not work so we can add it to the d…
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This appears to be a blocking thread. On a large filesystem where symlinks in the tree result in many files being indexed (about 10k) results in it hanging. Make this a background task or time limit…
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`clock` and `reset` signals must be made explicit to implement following new features.
* #624
* #623
* #569
Introduce special data type `clock` and `reset` types for this purpose.
```system…
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**Is your feature request related to a problem? Please describe.**
Currently, there doesn't seem to be a warning for binary operation width mismatches, which could be a good feature when using Slan…
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I try to export document from Obsidian to epub.
If I use bash code syntax — it is highlighted. If I use shell, nginx syntax for code blocks, it is not highligted.
Besides I tested export to pdf wi…
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Tokens are used in the IR to order side-effecting operations. Cover, assert, and trace nodes take and produce tokens but the underlying RTL implementations of these operations cannot be ordered. Token…