-
Ages ago, I proposed a Clang patch to add builtins for CSR accesses, so that there would be less reliance on inline assembly. I intended to finish that patch, and then make a proposal here, but I have…
-
To ensure that enough gas is available for executing the Safe transaction on deployment (which is required so that other wallets can properly estimate the required gas) it should be possible to specif…
-
Split out from https://github.com/ziglang/zig/issues/2081#issuecomment-751426901 . See also #5241 for inline assembly improvements.
# Zig Native Assembler
For system interfacing without libc in LL…
ghost updated
3 years ago
-
**Is your feature request related to a problem? Please describe.**
To reduce the number of redundant cpu cycles used in BlockingWaitStrategy's `waitFor()` function, it would be good to add a hint tel…
m0wfo updated
3 years ago
-
https://rcore-os.github.io/rCore-Tutorial-deploy/docs/lab-1/guide/part-4.html
-
Hii, I want to add an ISR to a PULPissimo application,I am using the sdk, I tried using the __attribute__((interrupt)) together with rt_irq_set_handler( ) and it works for ISRs that don’t contain func…
-
Hi,
The new ML algorithms in v1.5 are really impressive. It looks like they're only for implementations of OPUS that are Floating Point.
I'm compiling here for Xtensa LX6 (ESP32) which doesn't …
-
[Job](https://mihubot.xyz/runtime-utils/Ee56r-aAAAE) completed in 18 minutes 14 seconds.
### Diffs
```
Found 266 files with textual diffs.
Summary of Code Size diffs:
(Lower is better)
Total byte…
-
[Build](https://mihubot.xyz/runtime-utils/747a262463cb48e78c143d7a5d8b75c7) completed in 1 hour 41 minutes.
### Diffs
```
Found 315 files with textual diffs.
Summary of Code Size diffs:
(Lower is …
-
I haven't quite figured out what triggers the erratic behaviour but for some functions I'd get something like:
```
# cargo asm --rust core::ptr::real_drop_in_place
bx lr
_ZN8cortex_m10periph…