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I wanted to simulate the core to view wave forms of different instructions. But i am struck. I am getting this error "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from …
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**Using the Vagrant tutorial**
vagrant@precise64:~/chisel-tutorial/hello$ make
set -e -o pipefail; "sbt" -Dsbt.log.noformat=true -DchiselVersion="2.+" "run Hello --genHarness --compile --test --backe…
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**Issue by [zignig](https://github.com/zignig)**
_Tuesday Jun 25, 2019 at 00:21 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/108_
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Platform example ( simplified version of…
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Earlier on in one of these issues, I reported that same "canary" fail, which was solved by updating mpv to the latest version, 0.34.1. Trying same test as you did above:
```
# mpv --no-video --ao=…
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Hello,
Thank you for opening an issue. Please note that we try to keep the Terraform issue tracker reserved
for bug reports and feature requests. For general usage questions, please see:
https://…
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spike --dump-dts shows no DT info but the help screen.
Is this the expected behavior or am I doing something wrong?
```
spike --dump-dts
usage: spike [host options] [target options]
Host Opt…
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The simulation seems broken for the tutorials.
`aiecc.py` does not generate the `sim` directory inside `aie.mlir.prj/` by default with the `make` command as mentioned [here.](https://github.com/Xil…
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Hello @enjoy-digital,
I want to simulate the bare metal demo application on RISC-V cv32e41p and I had this bug of no prompt response.
However, it works fine with the cv32e40p core.
(The litex …
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### Version
Yosys 0.24+10 (git sha1 69cbef966, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
When a SystemVerilog code contains an interface with …
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### Describe the bug
@bwuch
I have tested and followed run script second time failed #530. but it seems got another error see update in #530 and made this error.
I got error when I run command Ge…