XDC Tutorial

[NyloxtheBard]

References the XDC tutorial

Formatting issue - Not generating the User interaction material, hard to understand what is going on with the lab, extremely unclear what the learning outcome is supposed to be. -The instructions for what each part does seem fine, although better clarification as to what we are editing for the Compiling with the F4PGA Toolchain could be better as it doesn't actually allow any edits currently -Should be renamed to properly highlight what it is, acts like a lab, not really a tutorial if following the standard that has been given for this notebook -The bit system on line Compiling the Lab with the Toolchain fails, which in turn causes the zip file to not be created. Everything past this point needs better documentation as well, as even if the zip file were created, I wouldn't know what it should be used for as the instructions for that are unclear. -The entire tutorial in general is not user friendly or interactive, is very unclear what is happening, and still fails to generate the zip file at the end despite going through the rest of it. I learned nothing from this tutorial, and honestly a complete rework of this section would be recommended.

[wirthlin]

Why is the title "Dataflow System Verilog" in the notebook but the name of the tutorial is "XDC"?

[jamilkhalaf]

I encountered a similar issue while attempting to run the XDC tutorial. Compilation errors arose because the convertData file was not located in the correct directory. Upon relocating it, I also adjusted the import source for the text, as the XDC tutorial was originally importing it from seven_segment_lab, while there was another import_all file in its directory. Despite resolving these issues, a new error persisted, indicating a permission denial to create the directory (/content/vcd).

The sequence of the lab is somewhat unclear to me. Initially, it provides an XDC code without demonstrating how to use it or which parts to uncomment. Subsequently, it abruptly transitions from the XDC code to a SystemVerilog code without clarifying the purpose or how it relates to our tasks.

Although labeled as a tutorial, halfway through, it feels more like a lab due to the lack of comprehensive explanations. It mentions utilizing the SystemVerilog code to uncomment necessary elements in the XDC file, but after compiling and running the code in the digital Colab, there is insufficient guidance on the specific actions we should take.