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Cocotb version 1.6.2
Ubuntu 18.04, 64-bit
ModelSim SE-64 10.6
Python 3.9.13 venv
I'm seeing an issue where concurrently awaiting for RisingEdge and FallingEdge on the same clock causes either or…
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**Description**
As part of the test case '_test_service_checker_with_process_exit_', 'syncd', 'database', 'bgp' and 'swss' containers need to be ignored. 'bgp' and 'swss' containers are ignored…
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I've been using cocotb for the past 6 months and have been progressing well with it. Generally learning it by following the examples and the unit tests in conjunction with the source
However I've com…
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This is surprising; I would have expected `poke`s to happen "immediately", typically aligned with the rising edge of the clock in a trace. Is there an option to enable this? As it is now, it's quite a…
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### Bug Description
I found the suspend failed sometimes because of "rtcwake: /dev/rtc0: unable to find device: Operation not permitted".
This problem was observed before, See Checkbox issue: ht…
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Add ability to OrignSim to be able to execute a task from the compiled RTL.
e.g.
~~~ruby
def call_my_func
tester.call "test.dut.my_ip.my_block.my_func", 1
end
~~~
I dont mind helping…
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It would be very useful to add constraints to only parts of a UVM hierarchy. For example, if we were to have a DUT with two AHB interfaces, we might want to constrain them individually. Global constra…
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cocotb version: 1.8.1
smulator: VCS
Python: 3.9.17
Hi, I am using cocotb to run some verification task right now. I intended to use interface in Verilog top.
It's ok in my python script to acces…
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Hi, I think I've hit a bug similar to #3078 , but a bit more difficult to trigger.
I've got a mixed-language design with both verilog and VHDL modules. For this particular case the path looks like th…
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```
Requested by user laikimfai (Philip) as a comment on the FAQ wiki page
(http://code.google.com/p/ostinato/wiki/FAQ)
Looking forward to BGP features
```
Original issue reported on code.google.…