Origen-SDK origen_sim issues

Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation

MIT License

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issues

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Fix hard coded pin paths at different locations making use of the testbench_top variable

#59 mathieuperret01 opened 1 year ago
3
task execution capability

#58 redxeth opened 1 year ago
3
Bump tzinfo from 1.2.5 to 1.2.10

#57 dependabot[bot] opened 2 years ago
0
Bump nokogiri from 1.10.5 to 1.13.4

#56 dependabot[bot] opened 2 years ago
0
Bump nokogiri from 1.10.5 to 1.13.3

#55 dependabot[bot] closed 2 years ago
1
Bump nokogiri from 1.10.5 to 1.12.5

#54 dependabot[bot] closed 2 years ago
1
OrigenSim documentation feedback

#53 jiangliu23 closed 2 years ago
2
Bump nokogiri from 1.10.5 to 1.11.4

#52 dependabot[bot] closed 2 years ago
1
Add ability to drive async clks during simulation

#51 ginty opened 3 years ago
5
tcl_inputs not working in environment as documented, need override

#50 redxeth opened 3 years ago
1
Bump json from 2.2.0 to 2.3.1

#49 dependabot[bot] opened 4 years ago
0
Bump nokogiri from 1.10.5 to 1.10.8

#48 dependabot[bot] closed 3 years ago
1
Increase match loop resolution

#47 ginty closed 4 years ago
1
Bump rubyzip from 1.2.4 to 2.0.0

#46 dependabot[bot] opened 4 years ago
0
Bump nokogiri from 1.10.3 to 1.10.5

#45 dependabot[bot] closed 4 years ago
0
Timing update

#44 pderouen closed 4 years ago
1
Misc patches

#43 ginty closed 4 years ago
0
Reg fail info

#42 pderouen closed 5 years ago
0
Add a warning when app OrigenSim version is behind the DUT Version

#41 ginty opened 5 years ago
1
Fixed issue reporting status of read only bits in failed transactions

#40 ginty closed 5 years ago
0
Crashes when an rc_dir_url is first added

#39 ginty opened 5 years ago
0
Bug fixes

#38 ginty closed 5 years ago
0
Empty log lines in -verbose mode

#37 ginty closed 5 years ago
1
Update to support long logger messages to the VPI. Messages need to b…

#36 coreyeng closed 5 years ago
3
Concurrent

#35 ginty closed 5 years ago
0
Adds WREAL Support

#34 ginty closed 5 years ago
3
Invalid pin X state reporting

#33 redxeth closed 5 years ago
0
Attempt to fix startup race conditions

#32 ginty closed 5 years ago
1
Name of 'module' needs to change when filename name is changed

#31 chrisnappi opened 5 years ago
1
Improved Debugging

#30 ginty closed 5 years ago
7
Add ability to change the capture directory

#29 ginty closed 5 years ago
3
Prevent sim monitor stopped errors during legal shutdown

#28 ginty closed 5 years ago
1
Error out if sim:pack or sim:unpack argument missing

#27 chrisnappi opened 5 years ago
3
Built in source sim

#26 coreyeng closed 5 years ago
4
Add pin monitors & correct a few bugs

#25 pderouen closed 5 years ago
9
Multi-line comments and other general improvements

#24 ginty closed 5 years ago
4
Sim Delay discussion

#23 priyavadan closed 5 years ago
1
Target vs. Environment for snapshots

#22 coreyeng closed 5 years ago
2
Ignore case when matching log lines

#21 ginty closed 5 years ago
4
Artifacts

#20 coreyeng closed 6 years ago
9
Match loop support and other improvements

#19 ginty closed 6 years ago
1
Cadence simulations running out of tmp/

#18 coreyeng closed 6 years ago
3
Verdi support

#17 priyavadan closed 5 years ago
9
Add support for Verdi

#16 priyavadan closed 5 years ago
1
VCS: New version, deprecated options

#15 priyavadan closed 5 years ago
1
Support more wave events

#14 ginty closed 6 years ago
1
Ruby crash should be reported as a simulation fail

#13 ginty closed 6 years ago
1
Add Support for LSF and Parallel Simulations

#12 ginty closed 6 years ago
4
Generic socket2 - Merged Generic Socket with master and added some features.

#11 coreyeng closed 6 years ago
4
Generic socket

#10 coreyeng closed 6 years ago
4