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Currently, if a field in a Grand Central-generated interface conflicts with a Verilog keyword, this will get mangled properly during `HWLegalizeNames`. However, this will not update the XMR that has a…
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Since SpinalHDL seems very similar to Chisel, I think it would be useful to provide a detailed comparison. The only thing I can find is an archived [Reddit thread](https://www.reddit.com/r/chisel/comm…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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Currently, if you try to data tap into the current module, the generated XMR will have no hierarchy. I don't think this will resolve correctly. Instead, there should be an additional level of hierar…
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I'm attempting to get this set up with LazyVim. I've confirmed that `neotest-rspec` is installed and that the ruby `nvim-treesitter` parser installed. However, I'm getting an "No Tests Found" message …
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Running following fir file
```python
; seed: 3339
circuit top_mod :
module top_mod :
input clock1: Clock
input inp_a: {inp_c: SInt, inp_f: {inp_g: {inp_j: SInt}}, inp_h: {inp_k: UInt…
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We started handling this in the parser so that we wouldn't have to worry about it for all the FIRRTL passes. This should fairly straightforward to remove, as no pass is generating or relying on this …
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When I am running a code for testing in fixedpoint, I am getting an error. Can anyone help me with the code???
Code:
package mypack
import chisel3._
import chisel3.util._
import chisel3.experime…
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Consider the following:
```scala
import chisel3._
import chisel3.experimental.dataview._
class Foo extends Bundle {
val foo = UInt(8.W)
}
class Bar extends Foo {
val bar = UInt(8.W)
}…
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…