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OS system : Ubuntu 22.04 ( Vivado v2024.1 64-bit )
project release : commit cdca76bbeebe8ea02333fd41829ffdf69d21a03c ( Linux kernel 6.9.6 )
project build : make CONFIG=rocket64b1 BOARD=arty-a7-100t…
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Some aarch64 machines (typically consumer machines that may need support for 32-bit apps) support 32-bit instructions, others (typically servers) don't.
This is hard to express in the archpolicies[…
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This tracks the status of s390x vector facilities support in rustc and standard libraries.
- ABI support
- [ ] support z13 vector ABI
https://github.com/rust-lang/rust/blob/9e394f551c050ff03c…
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The spec opens with the following words (although it is not the only section with clarified pronunciation in the specs):
> RISC-V (pronounced “risk-five”)
This is only of limited use, especially…
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LLVM code is tag llvmorg-15.0.4, build for RISC-V target.
```shell
cmake -G "Unix Makefiles" -DGCC_INSTALL_PREFIX=/data/dushaomin/task20221114/installtest20221128 -DLLVM_ENABLE_PROJECTS="clang;clan…
dshm updated
5 months ago
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There is a new risc v core named Xiangshan ([github](https://github.com/OpenXiangShan/XiangShan) ) written in chisel. Is it possible to have it in chipyard? Will it be useful for chipyard and/or xiang…
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Hi,
I am currently trying to evaluate the performance of doing some crypto on SERV, but I'm running into some issues with Zephyr on SERV.
I wrote the attached example (main.c) that just initiali…
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As some may be aware, there has been significant development and change on Microkit outside of the mainline version. This currently lives [here](https://github.com/Ivan-Velickovic/sel4cp).
This iss…
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# Description
```
mateusz@test:~/tb/github/mtkcpu$ riscv-none-elf-gdb -x board/breakpoint_example.gdb sw/uart_tx/build/uart_tx.elf
GNU gdb (xPack GNU RISC-V Embedded GCC x86_64) 13.2
Copyrigh…
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Exactly what it says in the title; the RISC-V overlay doesn't seem to exist...