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The current docs say
The RV32E calling convention may only be used with the RV32E ISA, hence the role of registers x16-x31 and f0-f31 is not defined. A future version of this specification may relax …
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I do this comand :
./configure --prefix=/opt/riscv --enable-multilib
make linux
and i have that issue:
checking for C compiler default output file name...
configure: error: in `/home/edgar…
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`I` and `E` is different base extension, however `E` is just kind of reduced register version of `I`, but `E` corresponding to which version of `I` seems like a problem.
The immediate problem is: …
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Hi,
I set XLEN=32 for whole system, so I intend to run 32 bit ELF on that system.
I just modify Makefile(in project-template/tests/)configuration to generate 32 bit ELF file.
revision part:
GCC=…
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According to https://github.com/cliffordwolf/picorv32/issues/92 picorv32 RISC soft core runs on Alhambra board. Is it possible to add support for this to FPGArduino?
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Dear experts,
We have an hardware architecture "rv64imafd". I tried the riscv-non-gcc to compile bare metal programs for this program. I coudnt succeed. Eventually I found out there is no multilib …
ghost updated
5 years ago
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I'm not a native English speaker so I am sorry for my poor expression :).
I have tested ```darkriscv``` by running test codes from ```https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui```.…
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Tried out on clash 0.99.3
$ clash --verilog System.hs
Prog.hs:4:1: error:
Could not find module ‘RiscV.RV32I’
Use -v to see a list of the files searched for.
|
4 | import RiscV.RV32…
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```
checking whether to use expat... yes
checking for libexpat... no
configure: error: expat is missing or unusable
Makefile:9095: recipe for target 'configure-gdb' failed
make[2]: *** [configu…
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Hi,
For one core which only supports RV32I, all of the control transfer instructions(jump and branch) would raise a misaligned instruction fetch exception if the target address is not aligned to f…