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**Environment:**
- OS: Windows 10
- SW Version or git tag: 217014d
**Describe the bug**
Kuiper Imager says that it successfully configured the zynq-coraz7s-cn0501 project from the ADI Kuiper I…
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I have been trying to recreate models that can be deployed effectively on the ZCU104 Ultrascale+ MPSoCs (Zynq Platforms). These are CNN models for CV task such as classification and object detection.
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Examples that are considered correct
`@STRUCT;1`
HEADER="STRUCT;1"
`@STRUCT=1`
FIELD_NAME="`@STRUCT`"
VALUE="1"
`INT1===1`
FIELD_NAME="INT1=="
VALUE="1"
`@2STRUCT1`
Whether the first…
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Hello,
I'm having some trouble to use FINN with my own network. I already followed the tutorial scripts which worked fine.
My network is not composed of fancy layers, only conv, batchnorm, Relu dans…
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Hello
i use ESP32 with SDIO interface (not connected now to host).
Connect to ESP-Bridge AP from windows computer and receive 192.168.4.2 address.
Try open web page from 192.168.4.1 and see status
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0. Could you send email to xianjun.jiao@ugent.be to introduce your self?
1. Our image is used directly or you build your own image?
your image directly.
2. What is your own modification?
no modi…
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Thanks for the demos.
Do you have a block design in Vivado for the SEA board demo example? If so, could you please export it to a tcl file and upload it to the repository?
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Hi! I have Vivado 2015.4, and I managed to do all up to the step:
- * Finally goto zynq_example\zynq_example.srcs\sources_1\ipshared\xilinx.com\processing_system7_bfm_v2_0\xxxxxxxx\hdl
For this st…
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I've seen Issue #489 and #592 but I can't resolve. (Sorry, I can't write ruby)
![Picture 3](https://github.com/mistydemeo/tigerbrew/assets/85050558/1bc0da41-336b-49a5-b8d8-3b72aa67bdd3)
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Hey,
Did you ever try to run proteus on FPGA boards like the Xilinx VCU-118? Is it mature enough to try that?