-
Reported by our colleagues from IDS:
> Sometimes, combinations of languages are listed as a single language (e.g. “Deutsch, Englisch”, “Deutsch ; Englisch”).
-
#327
[Adopting Multi Root Workspace APIs · microsoft/vscode Wiki](https://github.com/microsoft/vscode/wiki/Adopting-Multi-Root-Workspace-APIs)
-
To ease maintainability, it would make sense to merge `FABulous_project_template_verilog` and `FABulous_project_template_vhdl` into a single `FABulous_project_template`.
Many files in both director…
-
> https://twitter.com/mithro/status/1426666143914217474
>
> Check this out @mithro / @unaimarcor … we could base the HDL images on CentOS and use the already existing pre-built packages. Cristian is…
-
I often encounter some methods like Stream.s2mPipe() that I don't know what to do.There are very few comments in the source code, and most methods have no comment.I can only find part of the explanati…
-
The [project file](https://github.com/emard/galaksija/blob/master/proj/lattice/galaksija_ulx3s_hdmi/galaksija_hdmi.ldf) in `galaksija\proj\lattice\galaksija_ulx3s_hdmi` fails with error:
```
Start…
-
LSP v3.17 adds [subtypes](https://microsoft.github.io/language-server-protocol/specifications/lsp/3.17/specification/#typeHierarchy_subtypes). Is it possible to support them in VHDL-LS?
I am experi…
Nabav updated
4 months ago
-
if using the cheby-generated AXI4-Lite interface in Vivado block design without a wrapper following issues arise:
* the naming of the interface does not follow usual scheme of `[MS]_AXI_NAME`, inst…
-
For large verilog "Top" file which contains lot of modules instantiations,
it will be great to have a list of the modules used inside this file and easily navigate through the file.
Maybe click on l…
-
```
This is a fork of issue 99 where relevant aspects have previously been
discussed. Here some relevant comments.
---
#1 richard.eckart
I have added mapping files for NEGRA grammatical functions …