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Is SystemVerilog's atoi() function supported by Icarus? This example seems to fail, the error signature is:
- "No function named a.atoi found in this context"
```
module tb;
string a;
initial…
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Mangling user configuration without asking (*especially* the channel list and the `always_yes` setting, but disabling `changeps1` setting as well) is user-hostile. Using system/user channels in the Sy…
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I would like to investigate running Clash ... but (let's say) I don't have root on my target workstation. In the past with other systems I have been able to run a binary distribution in a local prefi…
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Let's suppose I have a Flip-Flop with a gated clock.... I'm using the code below in an FPGA to reset my flip-flops... (this works in an FPGA synthesis compile because Flip-flops default to zero state…
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Using always @* for constant assignments is giving me trouble in v11_0:
```
module test ();
reg y;
always @* begin
y = 1'b0;
end
initial begin
#1;
$display("Value of y: …
bfg86 updated
3 years ago
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I was working on a Verilator VPI test and comparing against iverilog when I hit this:
```
Program terminated with signal SIGSEGV, Segmentation fault.
#0 0x000055a214e6cc91 in vpi_free_object ()
w…
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Icarus Verilog master, reporting ``SIM_VERSION`` "11.0 (devel)", now supports bit selects (see https://github.com/steveicarus/iverilog/issues/323), so we should specify the affected versions in https:…
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I am trying to assign value to an input array.
```
input [7:0] src [0:1023];
```
I tried using this syntax
```
# Assign a value to a memory deep in the hierarchy
dut.src[0]
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IVL 12.0 devel. Using string argument with default value gives error:
> ../ivl_i390.sv:17: assert: PFunction.cc:47: failed assertion statement_
```verilog
package test_pkg;
virtual class…
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Hi!
Lots of changes have happened in iverilog since its last release. This means that most Linux distro packages are out of date. When can we expect a new release?