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Hi Sergiu,
I get the following error on running c simulation for nnet.cpp in Vivado HLS (windows 10) if I use the testbench directly.:
Couldn't open ref/fc_layer3_py.out@E Simulation failed: Funct…
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As far as I understand, the [config.json](https://github.com/hanchenye/scalehls/blob/master/samples/polybench/config.json) file has information about the target FPGA (number of DSPs etc) that are used…
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With the following Verilog input, targeting the Nexys A7-50T dev board with a xc7a50tcsg324-1 FPGA, the four LEDs should cycle between different single LED lighting up at roughly 1 Hz. With Vivado, th…
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I'm trying to build `Vitis_Libraries/vision/L2/examples/resize`. Following line does not work on newer GCC versions like `10.2.0`:
https://github.com/Xilinx/Vitis_Libraries/blob/eff2d5dd627c8d6c7ef…
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My system is Centos 7. My ISE is 14.6 and Vivado is 15.2.
I have already succeeded in generating the bitfile of the project NIC_1G_CML.
Yet I got an error when try to generate the bitfile of referen…
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Hello! I will be very greatful for any help.
I am trying to run 'switch calc' tutotrial.
I have set enviromental variables, created command.txt file and generated the resulting HDL files.
Now wh…
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Hello,
My project relies on the control plane writing the right data into registers. Therefore, in order to be able to test the functionality in the simulation, I would need to be able to write int…
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Hello,
Ran into the same issue you were having when you created this repo. Tried out your repo to see if it might happen to work for me and ran into this issue.
```
ERROR: [Common 17-70] Appli…
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The HLS report from AOC indicates that the CONV layer in BNN design is not pipelined because of some "Unsolvable exit condition". Here is the HLS report and the reduced test case (i.e. single layer CO…
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我注意到您生成了完整的二进制容器文件并打包成了overlay,这就意味着您在HLS里完成了从仿真到综合的一系列过程。想请教您testbench是如何编写的?