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The ForceNames annotation changes the name of modules after the creation of the verbatim ops, so we should be using symbol references to get the correct module names.
(this is just a tracking issue…
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Currently when you run `firtool --verbose-pass-executions`, it doesn't print any information when it's in the parser. This can be confusing to a user especially for large designs where, currently, >5…
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When we specify an output file for `repl-seq-mem` we should always output the conf file even if its empty.
Relevant line of code here: https://github.com/llvm/circt/blob/eafba50792dca320c0361e3eafd…
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InferResets uses `fieldRef`s to track specific reset element types in aggregates. There is a mismatch in that `fieldRef`s were not designed to track specific elements types in an aggregate type, but v…
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For example, object Mux will eventually call the pushCommand function in chiselFrontend/internal/Builder.scala. However, pushCommand calls the addCommand function in UserModule. Scala by adding Comman…
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Hi,
I want to ask a few questions about using hammer with the chipyard.
1. Is it possible to skip using asap 7 calibre deck to perform synthesis?
`make buildfile` needs the deck file.
*I use `…
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after `make init`, i try to run and get failure:
```
../mill/mill XiangShan.runMain top.TopMain -td build --config DefaultConfig --full-stacktrace --output-file XSTop.v --disable-all --remove-asse…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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Dedup needs to be expanded to support `strictconnect` ops, handling them the same way it handles regular `connect` ops. This is not a huge issue because there are no strictconnect ops coming from Chi…
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The following IR causes the `--convert-std-to-handshake` pass to produce a segfault.
```mlir
module {
func.func @foo(%mem : memref) {
return
}
}
```
The cause is `https://github.co…