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There are lots of crates for handling various kinds of binary structures:
- https://docs.rs/bilge/latest/bilge/
- https://docs.rs/bitflags/latest/bitflags/
- https://docs.rs/bit_field/latest/bit_…
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Recently I've made a PR for RISC-V support to Microkit (https://github.com/seL4/microkit/pull/179) which means that Microkit now supports multiple architectures.
This means that we need a new toolc…
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### Skill Name
Assembly, asm
### Why?
A lot of low-level programmers have assembly coding as one of their main skills. It's a shame to not be able to showcase that.
### Reference Image
There are …
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LLVM code is tag llvmorg-15.0.4, build for RISC-V target.
```shell
cmake -G "Unix Makefiles" -DGCC_INSTALL_PREFIX=/data/dushaomin/task20221114/installtest20221128 -DLLVM_ENABLE_PROJECTS="clang;clan…
dshm updated
7 months ago
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external/flac/ has optimized code (using intrinsics rather than in .S files) for all the other architectures. we'll likely want something for risc-v's V extension.
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- :star: [UART C driver](https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/uart.c)
- [UART C driver](https://blog.y2kbugger.com/baremetal-riscv-renode-3.html)
- [RISC-V from scratch 3: Writing…
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Thanks for this action, it has sped up my builds by about 6x to get down to 10 minutes which is wonderful. I am setting up builds using QEMU for RISCV in Docker. I was able to propagate the environm…
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Nice RISC-V
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# Context:
To load a `.C` program to NEORV32 first we must compile it.
There are many alternatives to make this.
## Custom GCC location:
### Steps:
- First, download GCC custom with RISC…
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Motivated by #179 (and #180), I took a look on how the `cortex-m` crate deals with [assembly instructions](https://github.com/rust-embedded/cortex-m/blob/master/cortex-m/src/asm.rs), and most of them …