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May I suggest that you open for "Discussions" in the repository settings?
This would make for a more natural place to discuss issues as your project moves along, and you could possibly ask @MikePop…
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Could I use pyslang to parse the json format AST?or turn the json to systemverilog code?
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In SystemVerilog, a function with a default value is defined like this (declared similarly):
```
// Function: a
function void a(bit b = 1'b1);
endfunction
```
Natural Docs will not include the f…
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Currently, the testbench tests the module for a couple of inputs only. You should randomize the inputs and verify the output of the RTL modules against a reference model. The reference model can be a …
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IEEE plans on approving 1800-2023 early December, with publication around Feb/Mar.
I have several related pulls ready in a private area. Currently the draft standard is only available to certain o…
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This is a request for a common log interface in OSVVM as discussed in https://github.com/VUnit/vunit/pull/776.
Such an interface has already been released for VUnit and can be used to redirect VUn…
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Updated (3/3/22):
Issue might be resolved: I noticed that I needed to manually clic…
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(x-post to BSG Manycoree)
It seems unnecessary to have $display statements enabled for every simulation run. Printing information on every run can slow the simulator down, or clog with unnecessary in…
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Hello,
I am using CMake as my build system for RTL simulations.
Very often I have a scenario where I have a custom command that would generate Verilog files.
I am using custom_commands rather tha…
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Hi,
I try to add a foler to the excluding list as "folder_name/**', but it seems don't work. The output window of the vscode still shows the indexing informations. My platform is Windows.
And it s…