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basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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SRAM TSMC 40 nm
#688
amithmath
opened
1 week ago
0
Broken Links
#687
Subashkatel
opened
2 weeks ago
1
Adding handshake descriptions
#686
dpetrisko
opened
2 weeks ago
1
Add tests for bsg_serial_in_parallel_out
#685
OroArmor
opened
1 month ago
0
Add tests for bsg_two_fifo
#684
OroArmor
opened
1 month ago
0
Random Coverage Testing of bsg_fifo_1rw_large
#683
Asiadav
opened
1 month ago
0
Adding coverage testing for bsg_imul_iterative
#682
Asiadav
closed
1 month ago
1
Harden Xilinx memories
#681
dpetrisko
closed
1 week ago
1
bsg_dmc: are non-burst write operations supported?
#680
infinitymdm
closed
1 month ago
4
bsg_dmc_s timing parameters
#679
infinitymdm
closed
2 months ago
3
SRAM
#678
amithmath
closed
2 weeks ago
2
Update bsg_defines.sv for yosys
#677
dpetrisko
closed
3 months ago
0
bsg_dmc/bsg_dmc_dly_line_v3.sv: Fix missing include
#676
infinitymdm
closed
3 months ago
1
bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Fix variable order
#675
infinitymdm
closed
3 months ago
0
bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Variable used before declaration
#674
infinitymdm
closed
3 months ago
0
bsg_dataflow/bsg_fifo_bypass.sv: Fix incorrect port name
#673
infinitymdm
closed
3 months ago
0
bsg_dataflow/bsg_fifo_bypass.sv: Port/variable name mismatch
#672
infinitymdm
closed
3 months ago
2
Getting Started with BaseJump STL
#671
ShvetankPrakash
closed
3 months ago
4
Rename bsg_decode_thermometer
#670
dpetrisko
opened
4 months ago
0
Update ascii to rom to work with python 2/3
#669
dpetrisko
closed
5 months ago
1
Reusable module for IPOLY hashing logic
#668
tommydcjung
closed
6 months ago
2
fix bsg_tag_trace_replay
#667
tommydcjung
closed
7 months ago
0
Basejump 2.0
#666
BrendenPage
closed
7 months ago
2
Basejump2.0
#665
BrendenPage
closed
7 months ago
0
fix the issue that max_val_p cannot be set to 2^n
#664
RicoLi424
opened
9 months ago
0
Fix the issue that max_val_p cannot be set to 2^n
#663
RicoLi424
closed
9 months ago
0
bsg_mem_1r1w_one_hot_write_mask_bit/byte
#662
RicoLi424
opened
9 months ago
1
Update bsg_noc_pkg.v to remove `ifdef
#661
dpetrisko
closed
6 months ago
0
Updated bsg_mem modules and testbenches for depths of 0 and 1
#660
RobertCrist
closed
11 months ago
0
Updated bsg_cache for direct mapping
#659
RobertCrist
opened
1 year ago
0
Migrate file extensions from .v to .sv
#658
BrendenPage
closed
7 months ago
0
Adding VCS support to makefile.sim
#657
dpetrisko
closed
6 months ago
0
Updated bsg_cache parametrization for single sets
#656
RobertCrist
closed
11 months ago
5
bsg_rom_param
#655
dpetrisko
opened
1 year ago
0
Read/Write ordering in Cache2AXI
#654
farzamgl
closed
8 months ago
0
Added an optimized popcount TDM generator to bsg_misc
#653
klundblad
opened
1 year ago
3
Add en_i port to bsg_tag_master_decentralized
#652
dpetrisko
opened
1 year ago
0
Adding tag constraints
#651
dpetrisko
opened
1 year ago
0
Add .regression directory
#650
BrendenPage
closed
1 year ago
4
Missing comma (typo)
#649
mysoreanoop
closed
1 year ago
0
Adding SURELOG to list of synthesis tools
#648
dpetrisko
closed
1 year ago
1
Use integer division in bsg_mem_generator.py
#647
dpetrisko
closed
1 year ago
0
Add xilinx bsg_launch_sync_sync
#646
Yuan-Mao
closed
1 year ago
4
bsg_link FPGA implementation release
#645
gaozihou
closed
1 year ago
6
Release bsg_link FPGA implementation
#644
dpetrisko
closed
1 year ago
0
Update bsg_fsb_node_trace_replay.v
#643
dpetrisko
closed
1 year ago
0
Update bsg_barrier.v
#642
dpetrisko
closed
1 year ago
0
Update bsg_ascii_to_rom.py
#641
dpetrisko
closed
1 year ago
0
Merge testing PRs to master
#640
BrendenPage
closed
1 year ago
0
[bsg_cache] ready_o -> yumi_o
#639
tommydcjung
closed
1 year ago
8
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