bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv: Fix variable order

bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

http://bjump.org/

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Closed infinitymdm closed 3 months ago

infinitymdm commented 3 months ago

Reorder variable declarations so that addr_li is not referenced before its declaration. Fixes #674