This library is a comprehensive hardware library for SystemVerilog that seeks to contain all of the commonly used HW primitives.
See this paper docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf which describes the design and usage.
Please also see the BSG SystemVerilog Style Guide which describes many of the conventions used in this library, including the variants of the valid/ready handshaking protocols.
Note: bsg_misc/bsg_defines.sv contains many macros used by BaseJump STL. Make sure it is in your include path.
bsg_misc
Lots of digital building blocks, like counters, reset timers, gray to binary coders, etc.
bsg_mem
Portable SRAM and RF interfaces.
For standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines, sbox units, compare_and_swap, and array pack/unpack.
This is for asynchronous building blocks, like the bsg_async_fifo, synchronizers, and credit counters.
Note: for tapeouts, you will need to pay attention to the physical design and timing constraints for these components.
Network on chip implementations
Reusable Cache implementation
High speed off-chip communication link (over LVCMOS I/Os, can hit 1.2 Gbps per pin to FPGA).
Unidirectional off-chip high-speed source synchronous communication interface. (also used as FPGA bridge).
Open source portable clock generator (all-standard cell)
High speed SPI-like interface for configuration state
LPDDR1 Dram Controller and PHY. Requires advanced knowledge to tapeout.
Data, clock, and reset generator for test benches.
Mirrors the other directories, with tests.
Mirrors other directories, contains replacement files for specific process technologies.
Example usage of these modules can be found in the HammerBlade manycore repository, the BlackParrot Repository and the Basejump STL Testing repository.
Email: taylor-bsg@googlegroups.com