The variable addr_li is referenced before declaration in bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv. While in principle an HDL shouldn't have any problem with this, some compilers don't like it very much. Causes compile errors in Questa/Modelsim and Synopsys DC (and possibly others as well).
The variable
addr_liis referenced before declaration in bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv. While in principle an HDL shouldn't have any problem with this, some compilers don't like it very much. Causes compile errors in Questa/Modelsim and Synopsys DC (and possibly others as well).https://github.com/bespoke-silicon-group/basejump_stl/blob/2a7310619aaf47362be74fcd34125a99b82cd388/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_from_1r1w.sv#L65-L69
The easy solution is to move L69 up to before L65. This resolves errors in both tools.