bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Update bsg_dlatch.sv #705

Open dpetrisko opened 1 week ago

dpetrisko commented 1 week ago

Latches are recommended to use blocking assignments as they follow similar rules to always_comb. This doesn't affect the functionality here, but disable warnings in Verilator and Xcelium