A module to reduce 2D array?

[tommydcjung]

For example, if we have a signal

logic [els_p-1:0][width_p-1:0] data;

we want to have an output that is reduced by OR ...

wire [width_p-1:0] output = data[0] | data[1] | ... | data[els_p-1];

[dpetrisko]

https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_reduce_segmented.sv

I guess it would be this plus a transpose?

[tommydcjung]

Oh I see... I guess that's a 'row-major' reduce, as opposed to 'column-major' reduce.

[tommydcjung]

There is also this https://github.com/bespoke-silicon-group/basejump_stl/blob/master/bsg_misc/bsg_transpose_reduce.sv#L28

But the ports seem broken...