Reusable module for IPOLY hashing logic

bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

http://bjump.org/

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Closed tommydcjung closed 11 months ago

dpetrisko commented 11 months ago

Is it simple to go smaller than 16 banks? If so, may be worth it to support for tiny manycores / BP multicores

tommydcjung commented 11 months ago

Added bank 4 and 8.