Basejump2.0 is an effort to update the port lists of all the modules within the repo, adhering to the style standard for the group, mainly focusing on handshake naming conventions (moving ready_o/i signals to one of ready_and_x, ready_then_x, or ready_param_x when the convention is set by a parameter (see here for an example)).
Additionally, the file extensions have all been migrated to SystemVerilog rather than Verilog.
Basejump2.0 is an effort to update the port lists of all the modules within the repo, adhering to the style standard for the group, mainly focusing on handshake naming conventions (moving ready_o/i signals to one of ready_and_x, ready_then_x, or ready_param_x when the convention is set by a parameter (see here for an example)).
Additionally, the file extensions have all been migrated to SystemVerilog rather than Verilog.